From jt@fuw.edu.pl Wed Sep 9 13:05:41 1998 Followup-To: alt.lang.asm In-reply-to: steve mcadams's message of 9 Sep 1998 04:48:07 GMT Newsgroups: comp.lang.asm.x86,alt.lang.asm,microsoft.public.masm Subject: Re: Old-timer newbie needs books or something... Cc: steve mcadams Reply-to: jt@zfja-gate.fuw.edu.pl= (Jerzy Tarasiuk; remove the '=') References: <6t51a7$c48$1@winter.news.erols.com> Message-ID: From: jt@fuw.edu.pl (Jerzy Tarasiuk) Date: 09 Sep 1998 13:05:40 +0200 Organization: Warsaw University, Physics Department Lines: 58 X-Newsreader: (ding) Gnus v0.82 >>>>> steve mcadams writes: > I've written lots of assembler (PDP-11, PDP-8, Z80, NSC-PACE, IBM 370, > and others) but none for x86. I'm conversant with C and C++ and with ... > So I know I need some information to get moving but I'm not sure where > to find it; basically I need zero conceptual help but all the specifics > about x86. Any/all clues appreciated. tia. -steve There is some far similarity of PDP-11, Z80 and x86... 8086 (oldest of the family) has 8 "general purpose" registers (AX,BX,CX,DX,SI,DI,BP,SP) and 4 segment registers (CS,DS,ES,SS). It has also IP register - unlike PDP it is not accessible. Segment registers: addresses are segment:offset, each 16-bit, value is segment*16+offset (except Protected Mode is enabled on 286+ CPU-s), CS:IP is Instruction Pointer, SS:SP is Stack Pointer. "General" registers have special properties: first AX,BX,CX,DX have halves AL(low),AH(high), BL,BH, CL,CH, DL,DH; BX/BP/SI/DI can be used for addressing data (BP causes SS used instead DS which is usually default segment), also combined two of them (BX or BP + SI or DI, but neither SI+DI nor BX+BP) + offset, DS:SI and ES:DI are source and destination of string manipulation instructions (DS can be overrided, ES cannot), CX can be used as repeat or loop counter, AX (and eventually DX) is used by 8 (16) bit multiply and divide (note two multiply/divide opcodes for each size: MUL/IMUL, and DIV/IDIV, the second does signed operation), e.g. MUL CX means DXAX=AX*CX, MUL AH means AX=AL*AH, DIV DH means AL=AX/DH, and AH=AX%DH (DIV is two-result operation). AX and DX are also used for I/O (e.g. OUT DX,AL writes AL to byte port DX). Control transfer (jump,call,return) can be intra-segment (CS unaffected), or inter-segment (CS loaded from opcode or stack), special case of control transfer are interrupts - which may be opcodes (INT xx, xx=0..FF), result of external event (IRQ 0-15, translated by external hardware to INT number and put on bus, or NMI which causes INT 02), exception (divide error = INT 00; 286+ have more exceptions), debug trace (INT 01 when CPU finishes executing opcode if T flag was set _before_ the opcode - note is T flag is cleared INT 01 still occurs once more); call puts on the stack IP or CS and IP (so there are 2 RET opcodes), interrupt puts also flags (and usually clears I flag disabling IRQ-s), so it needs another opcode (IRET) to return. Conditional control transfers (also LOOP) are short (7-bit) jumps only. Flags: it is two-byte register (there are opcodes to move low byte to/from AH), upper contains I, T, D - direction of address change during string manipulation, O - arithmetic overflow, it can be checked by INTO (INT 04 if O), J[N]O (conditional jump), lower has Sign,Zero,Parity,Carry on bits 7,6,2,0, bit 1 is set, bite 3 and 5 are clear, and bit 4 contains Auxiliary Carry (A), which helps in packed BCD arithmetic: e.g. to convert 4 bits in AL to hex char, need: AND AL,0Fh (clear other bits), CMP AL,10, SBB AL,69h, DAS (the last opcode uses A set by SBB). Well, it is some introduction. For more info get opcode list, (ftp://zfja-gate.fuw.edu.pl/mail-ftp/zfja-ftp/cpu/intel.lzh) and programming manual (386intel.zip in same directory). There is also ncc.c, short Turbo-C program telling what CPU you have (distinguishes pre-286,286,386,486 by flags testing).