Protel Design System Design Rule Check
PCB File : PCB1.PCB
Date     : 25-Mar-2003
Time     : 02:14:36

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Rule Violations :0

Processing Rule : Width Constraint (Min=8mil) (Max=30mil) (Prefered=10mil) (On the board )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (On the board ) )
   Violation         Net GND   is broken into 7 sub-nets. Routed To 90.32%
     Subnet : J20-1    Y1-3     C8-2     C12-1    D1-1     U2-30    R7-2     U2-17    R12-1    C1-2     
              C7-2     D2-1     U6-6     U6-7     C2-2     C6-2     U3-6     U6-4     C40-2    C25-2    R25-1    
              C4-2     C13-2    C16-2    U7-6     U7-7     R35-1    U7-4     R6-1     S3-1     S1-1     S4-1     
              C41-1    U5-6     U5-7     L3-2     Y2-2     C21-2    R26-1    R36-1    R27-1    S5-1     U11-4    
              R9-1     C22-2    R16-1    U1-7     C17-1    U2-11    U21-5    C28-2    C29-2    C35-2    
     Subnet : U3-4     
     Subnet : C20-1    R34-1    
     Subnet : R17-1    C19-2    
     Subnet : C24-2    
     Subnet : U5-4     
     Subnet : C26-2    C34-2    C27-2    
Rule Violations :1

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0


Violations Detected : 1
Time Elapsed        : 00:00:08
